Simulation of Different Characteristics of CMOS Charge Sharing Dynamic Latch Comparator in 0.35μm, 0.25μm and 0.18μm Technologies
نویسندگان
چکیده
Abstract — The design and various analysis of low power, high speed CMOS dynamic latch comparator is presented. The comparator combines the features of both, the resistive dividing network and differential current sensing comparator. The proposed design will improve the comparator performance by reducing the propagation delay, power dissipation, offset with high ICMR. Simulation results are obtained in 0.35um, 0.25um and 0.18um with supply voltages of 2.5v, 2v and 1.8v respectively.
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تاریخ انتشار 2012